1. Field of the Invention
The present invention relates to a semiconductor storage device with a multiplicity of storage cells, arranged on a semiconductor substrate, for programmable storage of data contents. The semiconductor storage device can be operated in at least two operating states; the first of which is assigned to erasing the data content from a storage cell and the second is assigned to maintaining a data content of a storage cell. The semiconductor storage device can also be operated with a selection circuit for selecting an associated group of storage cells and with at least one drive circuit with a drive line, assigned to the storage cells, for selective application of either an erase voltage or a reference voltage to the selected group of storage cells.
2. Description of the Related Art
A main field of application of a semiconductor storage device of this type is constituted by nonvolatile electrically erasable programmable semiconductor memories which are constructed from storage cells that can be programmed and re-erased as often as desired by applying predetermined voltages. Information is, in this case, stored by supplying or removing charges to or from the so-called floating gate electrode. This is done by-applying suitable voltages to word and bit lines of the storage arrangement. In the case of read operating conditions with low voltages of, typically, about 5 volts, no charges can overcome the insulation potential barrier so that the charge, once stored, remains conserved. In contrast, in the case of programming and erasing, higher voltages of, typically, about 17 volts are applied between the control gate and the source/drain/substrate.
These voltages are also referred to hereafter as high voltages, since they exceed the supply voltage in terms of magnitude. Because of a high field strength, electrons can tunnel through the insulation potential barrier (Fowler-Nordheim effect) or hot electrons originating in the vicinity of the drain can overcome the insulation (channel hot electron effect). Since the supply voltage of the storage circuit is typically about 5 volts, it is necessary to provide drive circuits for the externally supplied or internally generated programming and erase voltages, which can selectively switch these voltages onto the storage cells (or word and bit line). On the grounds of considerations relating to circuitry and technology, it is advantageous to limit the voltage range at least of one drive line (bit line or word line) to less than or equal to the value of the supply voltage and to use high voltages only on the other drive line. As a consequence, both positive and negative high voltages must be switched selectively onto the lines for programming and erasing.
Y. Yatsuda et al., IEEE J. Solid-State Circuits, Vol. sc-20. No. 1., pages 144-151, 1985 discloses a high-voltage drive circuit for positive voltages, which uses an external clock. However, the circuit, formed by NMOS transistors, cannot switch negative high voltages. Furthermore, the circuit requires a relatively large capacitance C in order to be able to deliver a sufficiently large charging current in order that the load can be charged in a time of 50 to 100 .mu.s.
EP 320,916 EI has disclosed a drive circuit for a non-volatile electrically erasable and programmable semiconductor memory, which can switch both positive and negative high voltages and uses an external clock. This circuit is based on the principle of assigning each load its own high-voltage generator which generates the required negative high voltage. However, the number of generator stages required increases with the magnitude of the high voltage.
For higher voltage values, this design has a large area requirement. A further disadvantage is that in erase operation (negative high voltage), the known circuit does not, in the unselected case, deliver a clean zero volt level. In a preparatory phase, a precharge is applied with a predetermined voltage value to the load. During the actual erase process, the level is limited merely by the series circuit which includes an NMOS transistor and a plurality of PMOS transistors. As a result, the known circuit is also susceptible to interference due to crosstalk. In read mode (voltage+5 volts) and write mode (voltage+15 volts), the zero volt levels are likewise not clean. Instead of this, the output voltage is equal to the magnitude of a PMOS threshold voltage. The proposal of using a transistor with a threshold voltage of zero volts shifts the problem to a more complex and, therefore, less economical technology.
IEEE Journal of Solid-State Circuits, Vol, 27, No. 11, Nov. 1, 1992, pp. 1547-1553, XP000320441, Toshikatsu Jinbo et al., "A 5-V-Only 16 MB Flash memory with Sector Erase Mode" discloses a semiconductor memory means wherein a drive circuit as row main decoder is provided with circuit blocks A and B. The circuit block A, which is referenced as a conventional block, follows an nMOS depletion transistor for the high-voltage and is active during the program mode. The circuit block B for switching the negative voltage primarily serves for converting a positive-level signal into a negative voltage level of the erase mode. To this end, the circuit block B is charged with a negative high-voltage of -13 Volts from a charge pump circuit and is switched via a drive signal. This known drive circuit thus enables the selection of an individual word line and driving with a negative erase voltage, in addition to a drive with 5 V or, respectively, 0 V for the read mode. Although the function of the known drive circuit seems to be comparable to that of the inventive circuit, the underlying structural circuit concepts differ significantly from one another.
A further drive circuit for EEPROM memory cells has been disclosed by U.S. Pat. No. 4,823,318. This drive circuit also differs from the inventive drive circuit in terms of critical, specific features.
U.S. Pat. No. 4,742,492 has disclosed a further drive circuit whose purpose lies in supplying the voltages -Vgg, -Vpp and +Vpp generated by three charge pumps to a capacitor of the output side in alternation. To this end, respectively one of the three charge pumps is connected dependent on the control signal adjacent on an input line. This drive circuit also differs from the inventive circuit in terms of individual circuit details.
The object of the present invention is to provide a circuit arrangement, of the generic type mentioned at the start, which is simpler in terms of circuitry, requires less area, has a lower power consumption overall and has the least possible cross currents, and thereby supplies clean voltage levels, particularly smooth zero volt levels, in all operating conditions.